As speed requirements of computer systems have increased, systems employing greater numbers of parallel processors have been developed. One such system, has in the order of 64 parallel processors, see U.S. Pat. No. 3,537,074, issued Oct. 27, 1970 to R. A. Stokes et al., and assigned to the assignee of the present invention.
Present day large computer systems incorporating a high degree of parallelism often include a plurality of widely scattered registers. When data in these registers are to be compared, the propagation delays involved in transmitting data from each register to a central comparator and back consumes precious processing time and limits the overall throughput of the system.
Certain calculations in large parallel computer systems require the determination of which register(s) in a plurality of scattered registers are storing either the highest or lowest value numerical data. Bit-by-bit comparison of the data in the registers involves long propagation delays due to the repetitive cycling of data over long data paths. Conversely, comparison in parallel of the data in the registers is prohibitively expensive and complex due to the increased amount of logic and cabling required.
Therefore, it is an object of the present invention to provide an improved method and apparatus for determining selectively the register or registers storing either the highest or lowest value of numerical data in a plurality of widely scattered registers.
It is another object of the invention to minimize both propagation delay and circuit complexity in a system for determining selectively the register or registers storing either the highest or lowest value of numerical data in a plurality of registers.